Copper plated PTH barrels and methods for fabricating

ABSTRACT

A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

TECHNICAL FIELD

[0001] The present invention relates to circuitized printed wiring boardstructures and especially to via barrels having enhanced copperadhesion. The enhanced adhesiveness of the copper plating providesimproved performance in high temperature assembly operations. Thepresent invention also provides a method for fabricating via barrelsplated with highly adherent copper.

BACKGROUND OF THE INVENTION

[0002] In the manufacture of printed circuit boards, sometimes known asprinted wiring boards, it is now commonplace to produce printedcircuitry on both sides of a planar rigid or flexible insulatingsubstrate. Of increased importance is the manufacture of multilayerprinted circuits. In these products, the board consists of parallel,planar, alternating innerlayers of insulating substrate material andconductive metal. The exposed outer sides of the laminated structure areprovided with circuit patterns as with double-sided boards, and themetal innerlayers may themselves contain circuit patterns.

[0003] In double-sided and multilayer printed circuit boards, it isnecessary to provide conductive interconnection between or among thevarious layers or sides of the board containing conductive circuitry.This is commonly achieved by providing metallized, conductive thru-holesin the board communicating with the sides and layers requiringelectrical interconnection. For some applications, it is desired thatelectrical connection be made with up to all of the conductive layers.In such case, thru-holes are provided through the entire thickness ofthe board. For other applications, it is desired to provide electricalconnection between the circuitry on one face of the board and one ormore of the inner circuit layers. In those cases, blind via, passingonly part way through the board are provided. For purposes of thisapplication, the terms “thru-hole,” “blind via,” and “via” are usedinterchangeably.

[0004] To provide the desired circuit pattern on the board, the art hasdeveloped a variety of manufacturing sequences, many of which fall intothe broad categories of “subtractive” or “additive” techniques. Commonto subtractive processes is the need to etch away (or subtract) metal toexpose substrate surface in areas where no circuitry is desired.Additive processes, on the other hand, begin with exposed substratesurfaces (or thin commoning metallization layers for additiveelectroplate) and build up thereon metallization in desired areas, thedesired areas being those not masked by a previously-applied pattern ofplating resist material (e.g., photoresist in positive pattern).

[0005] Typically, via holes are drilled or punched into or through theboard structure at desired locations. Drilling or punching providesnewly-exposed surfaces including via barrel surfaces and via peripheralentry surfaces. The dielectric substrate, comprising a top surface, abottom surface, and at least one exposed via hole surface, consistingpartly or entirely of insulating material, is then metallized, generallyby utilization of electroless metal depositing techniques.

[0006] In the manufacture of circuitized printed wiring board carrierstructures, a dielectric sheet material is employed as the substrate.The substrate typically is an organic material, such asfiberglass-reinforced epoxy resin (FR4), polytetrafluoroethylene, etc.Since the dielectric substrate is nonconductive, in order to plate onthe substrate, the substrate must be seeded or catalyzed prior to thedeposition of metal onto the substrate. The electroless plating ofcopper onto a substrate is well-known in the art. For instance, anelectroless or autocatalytic copper plating bath usually contains acupric salt, a reducing agent for the cupric salt, a chelating orcomplexing agent, and a pH adjustor. In addition, if the surface beingplated is not already catalytic for the deposition of the desired metal,a suitable catalyst is deposited onto the surface prior to contact withthe plating bath. Among the more widely employed procedures forcatalyzing a surface is the use of stannous chloride sensitizingsolution and a palladium chloride activator to form a layer of metallicpalladium particles.

[0007] Copper is not highly adherent to the materials typically used asthe dielectric substrate. The deposited copper is generally anchored tothe exposed inner copper layers more than the dielectric. Duringsubsequent process steps, especially thermal cycling, the copper“barrel” has a tendency to crack or delaminate, causing open circuits.Therefore a requirement exists for means to increase the bondingstrength of the copper to the substrate.

[0008] The present invention provides the desired increased durabilityof via barrels without the requirement for many of the additionalprocessing steps and materials used in prior art solutions. For example,Takahashi et al. (U.S. Pat. No. 5,309,632) require a double resistprocess and the application of an adhesive layer to the entire boardsurface. Their method also plates nickel over the entire board surfaceand then strip the nickel in excess of the circuitization.

[0009] It is known in the prior art to provide a layer of nickel oversubstantially the entire surface of the wiring board, print coppercircuitization over the nickel, and then to strip excess nickel.Examples of this practice include Cane (U.S. Pat. No. 5,648,125).Stripping of Ni after application of Cu results in a line substantiallytrapezoidal in cross-section, with portions of the Cu wiringcantilevered, unstably over the Ni. In addition to plating Ni only wherecircuitization is to be invoked, the process of the present inventionresults in lines of substantially rectangular cross-section and thus amore stable bonding of the Cu.

[0010] Another disadvantage of prior art methods is exemplified by Knopp(U.S. Pat. No. 5,758,412) where the thickness of the underplated metalis too thin to provide circuitization robustness against subsequent hightemperature assembly steps.

SUMMARY OF INVENTION

[0011] The present invention provides via barrels exhibiting high copperto substrate adhesion. The present invention makes possible via barrelsthat survive the thermal stresses of high temperature assembly and havea longer thermal cycle life than bare copper barrels.

[0012] More specifically, the present invention provides via barrelswhich comprise: a wiring board of dielectric material wherein aplurality of via are defined; a catalyst seed layer located on the innersurface of the via within the dielectric material; a layer of nickeldeposited on top of the catalyst seed layer; and a layer of copperplating in the openings and over the layer of nickel.

[0013] It is an aspect of the invention to provide more robustmetallization of via barrels by providing multiple metallization layers.

[0014] It is an aspect of the invention to provide more robustmetallization of via barrels by providing metallization, of via barrelsurfaces including via peripheral entry surfaces, and providingmetallization of via surfaces continuous with metallization of the topand bottom surfaces and the conductive layers of the dielectricsubstrate.

[0015] It is an aspect of the invention to provide more robustmetallization of via barrels by providing a circuitized printed wiringboard comprising a dielectric substrate having a top surface, and abottom surface, and at least one via, the at least one via having a viabarrel surface and at least one via peripheral entry surface; a firstmetallization layer deposited on the via barrel surface and the at leastone via peripheral entry surface of the at least one via, the topsurface, and the bottom surface of the dielectric substrate; a secondmetallization layer deposited on the first metallization layer on thevia barrel surface and the at least one via peripheral entry surface ofthe at least one via, and selectively deposited on the firstmetallization layer on the top surface and the bottom surface of saiddielectric substrate; and a third metallization layer deposited on thesecond metallization layer on the first metallization layer on the viabarrel surface and the at least one via peripheral entry surface of theat least one via, and selectively deposited on the second metallizationlayer on the first metallization layer on the top surface and the bottomsurface of the dielectric substrate.

[0016] The present invention also relates to fabricating the abovedisclosed printed circuit board. The method comprises: providing a boardhaving a top surface and a bottom surface and comprised of one or morelayers of dielectric material and optionally one or more innerconductive layers which are optionally personalized by provision of apattern such as a circuit pattern; depositing a catalyst seed layer onthe layer of dielectric material; depositing a layer of nickel on top ofthe catalyst seed layer; and depositing a layer of copper plating overthe layer of nickel.

[0017] Metallization of the dielectric substrate comprises providing afirst metallization layer termed a catalytic seed layer and is typicallypalladium and tin; providing a second metallization layer wherein thelayer is chosen from the group VIII and Group IB transition metals andis typically nickel; and providing a third metallization layer,typically copper. Alternatively, the catalytic seed layer is thus termedand the nickel and copper layers are respectively termed the “firstmetallization” and the “second metallization.”

[0018] Still other objects and advantages of the present invention willbecome readily apparent by those skilled in the art from the followingdetailed description, wherein it is shown and described only thepreferred embodiments of the invention, simply by way of illustration ofthe best mode contemplated of carrying out the invention. As will berealized the invention is capable of other and different embodiments,and its several details are capable of modifications in various obviousrespects, without departing from the invention. Accordingly, thedescription is to be regarded as illustrative in nature and not asrestrictive.

SUMMARY OF DRAWINGS

[0019] The invention is best understood from the following detaileddescription when read in connection with the accompanying drawings. Itis emphasized that, according to common practice, the various featuresof the drawing are not to scale. On the contrary, the dimensions of thevarious features are arbitrarily expanded or reduced for clarity.

[0020]FIG. 1 is a schematic cross-section of base member;

[0021]FIG. 2 is a schematic transverse section of base member followingformation of through hole;

[0022]FIG. 3 is a schematic cross-section of base member after contactwith catalytic composition;

[0023]FIG. 4 is a schematic cross-section of base member afterapplication of photoresist;

[0024]FIG. 5 is a schematic cross-section of base member after secondmetallization layer; and

[0025]FIG. 6 is a schematic cross-section of base member after thirdmetallization layer.

BEST AND VARIOUS MODES FOR CARRYING OUT INVENTION

[0026] Reference is made to the figures to illustrate selectedembodiments and preferred modes of carrying out the invention. It is tobe understood that the invention is not hereby limited to those aspectsdepicted in the figures.

[0027] In FIG. 1, there is shown an electrically insulative base member13 which may be used in the present invention to produce a printedwiring board (described below). It is understood that the invention isnot limited to the particular configuration shown in FIG. 1, as othersare readily possible. Base member 13 includes first and secondconductive layers 1 and 3, which sandwich there between, first andsecond dielectric layers 2 and 4 and conductive plane 5. In a preferredembodiment, each of the two conductive layers is comprised of copper ora well-known conductive material, each having a thickness from about0.25 mils (0.0025 inches) to about 1.5 mils with the thickness of eachpreferably being about 0.25 mils. Preferably each of the two dielectriclayers is comprised of fiberglass reinforced epoxy resin (FR4).

[0028] A typical FR-4 epoxy composition contains 70-90 parts ofbrominated polyglycidyl ether of bisphenol-A and 10-30 parts oftetrakis(hydroxyphenyl)ethane tetraglycidyl ether cured with 3 to 4parts of dicyandiamide, and 0.2 to 0.4 parts of a tertiary amine, allparts being parts by weight per 100 parts of resin solids.

[0029] Another typical FR-4 epoxy composition contains: a) about 25 toabout 30 parts by weight of a tetrabrominated diglycidyl ether ofbisphenol-A having an epoxy equivalent weight of about 350 to about 450;b) about 10 to about 15 parts by weight of a tetrabrominated diglycidylether of bisphenol-A having an epoxy equivalent weight of about 600 toabout 750; and c) about 55 to about 65 parts by weight of at least oneepoxidized non-linear novolak, having at least terminal epoxy groups,along with suitable curing and/or hardening agents.

[0030] Another typical FR-4 epoxy composition contains about 70 to about90 parts of brominated polyglycidyl ether of bisphenol-A, and 10 to 30parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with0.8 to 1 part of 2-methyl imidazole.

[0031] Still another FR-4 epoxy composition employs tetrabromobisphenol-A as the curing agent, along with 2-methyl imidazole as thecatalyst.

[0032] In alternative embodiments, a wide variety of dielectric(non-conductive) substrates can be employed and, as described in theprior art, include thermoplastic and thermosetting resins. Typicalthermosetting polymeric materials include epoxy, phenolic basedmaterials, and polyamides. The dielectric materials may be moldedarticles of the polymers containing fillers and/or reinforcing agents,such as glass-filled epoxy or phenolic based materials. Examples of somephenolic type materials include copolymers of phenol, resorcinol andcresol. Examples of some suitable thermoplastic polymeric materialsinclude polyolefins, such as polypropylene, polysulfones,polycarbonates, nitrile rubbers, ABS polymers and fluorinated polymericmaterials such as polytetrafluoroethylene.

[0033] In preferred embodiments, comprising FR4, each dielectric layerpossesses a thickness of from about 2 mils to about 20 mils. Thicknessesless than about 2 mils for this particular material may be undesirablebecause the resulting structure may be flimsy and difficult to handleduring subsequent manufacturing processes. Thicknesses greater thanabout 20 mils may be undesirable because such thick dielectric layers,in addition to requiring relatively large conductor line widths andthicknesses, also may prevent optimum package electrical performance.

[0034] Sandwiched between dielectric layers 2 and 4 is conductive plane5, preferably of copper or other well-known conductive material andpossessing a thickness of preferably within the range of about 0.125mils to about 2.5 mils. The thicknesses for plane 5 of less than about0.125 mils may prove undesirable should the resulting structure bysubjected to relatively high temperatures. Additionally, thicknessesgreater than about 2.5 mils may prove undesirable because of theadditional time necessary to form such layers using conventional platingtechniques and associated difficulties with line width control.

[0035] The resulting structure shown in FIG. 1 thus preferably possessesa thickness within the range of about 4.7 mils to about 400 mils. Thepreferred thickness is governed by the desired number of signal planes.

[0036] Conductive layers 1 and 3 and dielectric layers 2 and 4 arebonded to the conductive plane 5 using a lamination process, such aprocess known in the art and further description is not believednecessary.

[0037] Base member 13 is thus shown to include at least two surfaces, afirst surface 6, and a second surface 7.

[0038] Although two conductive layers and two dielectric layers areshown for base member 13, it is understood that the invention is notlimited thereto. Specifically, it is only necessary to provide one suchconductive layer and one such dielectric layer while still attaining theadvantageous results taught herein. At least two layers of each are usedwhen it is desired to incorporate an internal conductive plane (e.g.,power, ground or signal) as part of the final structure. Understandably,several dielectric layers and corresponding internal conductive planesmay be utilized, depending on operational requirements for the finishedproduct.

[0039] In FIG. 2, opening 8 having an internal wall surface or viabarrel surface 9 and having a via peripheral entry surface or knee 9A isformed substantially through base member 13. Although only one openingis shown formed in base member 13, it is understood that multipleopenings may be formed in base member 13 depending on the ultimateelectrical requirements of the circuitized substrate. Opening 8, whichmay be any type of via, may be formed by mechanical drilling althoughother hole forming techniques such as punching and laser drilling can beused. The minimum diameter of opening 8 is governed by the depth of thehole such that an approximately unitary aspect ratio (holediameter/depth) is achieved. The upper limit of hole diameter is afunction of the purpose of the hole.

[0040] In the next step, it is preferred to provide afirst-metallization layer 10 on the surfaces 6 and 7 of base member 13,and on internal wall 9 of opening 8 to act as a catalyst for futuremetallization layers.

[0041]FIG. 3 shows base member 13 after contact with a compositioncontaining a catalytic composition capable of initiating an electrolessplating process providing a catalyst seed layer 10. The catalyst seedlayer 10 is alternatively referred to as the first metallization layer.The compositions contain a metal that can directly provide the catalyticsites, or serve as a precursor which leads to the catalytic sites. Themetal present may be in the elemental form, an alloy, or compound, ormixtures thereof. The preferred metal catalysts are precious metals,such as gold, palladium, and platinum. A typical palladium compositioncontains about 1.2 to about 2.5 grams per liter of a palladium salt,which is preferably PdCl₂, about 80 to about 150 grams per liter of astannous salt, which is preferably SnCl₂.2H₂O, and about 100 to about150 milliliters per liter of an acid which is preferably HCl. When HClis provided in the form of a 37% HCl solution, about 280 to about 360milliliters of the HCl solution is preferably employed. The mostpreferred composition contains about 1.5 grams per liter of PdCl₂ andabout 280 milliliters per liter of 37% HCl. The composition is usuallymaintained at a temperature of about 65±10° F. A typical triple-seederprocess is disclosed, for instance, in Alpaugh et al U.S. Pat. No.4,525,390, disclosure of which is incorporated herein by reference.

[0042] Subsequently, the substrate can be treated with an acid oralkaline accelerator such as a 2% NaOH solution to remove excess tinwhich is typically deposited along with the Pd catalyst. This stepusually takes about 1 to about 5 minutes and, more typically, about 1 toabout 2 minutes.

[0043] The substrates can then be dried, such as by being vacuum driedin an oven for 30 minutes at a temperature of about 100° C. In thedrying operation, all the water is driven off irreversibly from thecolloidal particles, leaving a shell of oxygen in the form of insolubletin oxide.

[0044] Moreover, if desired, prior to providing the catalyst seed layer10, the dielectric layers 2 and 4 can be treated with an acidic solutioncontaining a multifunctional ionic copolymer containing at least twoavailable cationic functional moieties. The preferred ionic moieties arequaternary phosphonium and quaternary ammonium groups. Copolymerscontaining at least two cationic moieties such as, for example,copolymers of polyacrylamide forming the inert backbone and functionallyactive tetraalkylammonium compounds, are commercially available and neednot be described herein in detail. Multifunctional cationic copolymersof that type are Reten 210 and Reten 220, available from HERCULES,description of which can be found in “Water-Soluble Polymers”, BulletinVC-482A, HERCULES, Inc., Wilmington, Del., 1989, disclosure of which isincorporated herein by reference.

[0045] Reten 210 is in powder form and is a copolymer of acrylamide andbeta-methacryloxyethyltrimethylammonium methyl sulfate, of which a 1%solution has a Brookfield viscosity of 600-1000 cps. Reten 220 is alsoin powder form and consists of the same monomers as Reten 210, but its1% solution has a Brookfield viscosity of 800-1200 cps. The molecularweights of the Reten polymers are usually relatively high and vary fromabout 50,000 to about 1,000,000 or more. The quaternary ammonium groupsprovide the number of positive charges of the polymer.

[0046] In the various aspects of the present invention, the ioniccopolymer is employed as a dilute acidic solution of about 0.01% toabout 1% by weight, and preferably about 0.05% to about 0.5% by weightof the copolymer. The acid contained in the solution is preferablyH₂SO₄, and the pH value of the solution is between 0 and about 3. Theuse of a low pH value is preferred to obtain a relatively low viscosityof the copolymer solution to facilitate application of the polymer. Thetreatment with the ionic copolymer is generally about 1 minute to about10 minutes, and preferably about 1 minute to about 2 minutes, and takesplace at about room temperature.

[0047] The multifunctional copolymer, having a very good adhesion to thesubstrate surface, provides the surface with a charge opposite from thatassociated with the seed particles 10 applied to the substrate. Thisdifference in polarity provides for electrostatic attraction of the seedparticles. After the substrate is brought into contact with the ioniccopolymer composition, the substrate is rinsed to remove any excesspolymer not adhering to the substrate surface.

[0048] A layer 31 of photoimaging (photoresist) material is then appliedto the surfaces of member 13 over the first metallization layer. In oneexample, the layer of photoresist possessed a thickness of from about0.3 mils to about 2.0 mils. A preferred material is a positive-actingphotoresist, various examples being known in the art, including T168photoresist available from the E. I. du Pont de Nemours Corporationunder this trade designation. A positive-acting photoresists, whenapplied and exposed through a suitable photomask, undergo a physical andchemical change in the exposed areas that render these areas insolubleto the subsequent developing solution which is to be applied thereto.Following exposure, the resist-coated base member 13 is immersed indeveloping solution (e.g., benzyl alcohol or propylene carbonate), whichallows the unexposed areas to be removed without excessive impact on thehardened, exposed area. Baking or other processes may be used to furtherharden the remaining, exposed portions, if desired. With positive-actingphotoresists, the portions developed away form the openings to thecatalyzed laminated surface for subsequent plating

[0049] In FIG. 4, base member 13 is shown following the above exposureand removal (developing) operations. As such, only portions ofphotoresist layer 31 remain. These portions are represented by thenumeral 11. It is understood that the removed portions of thephotoresist in turn result in openings 35 which, in turn, exposepreselected areas on the respective surfaces on which circuitization isto eventually occur. Thus a predetermined pattern on both surfaces isprovided. Furthermore, it is understood that the photomask is designedsuch that the internal wall 9 of through holes 8 are not exposed.

[0050] As seen next, in FIG. 5, a second metallization layer 12 isdeposited into the photoresist openings formed on base member 13 and inthrough hole 8. The second metallization conductive layer 12 comprisesnickel. The thickness of this second metallization conductive layer maybe from about 0.1 mils to about 0.15 mils preferably about 0.12 mils toabout 0.13 mils. The nickel is deposited on the seed layer by immersinginto an electroless nickel plating process as known in the industry.Plating chemistries for electroless nickel plating are well known in theindustry and need not be described herein in any detail.

[0051] Typical methods for depositing nickel on the surface or surfacesof a substrate involve immersing the substrate in an aqueous solutioncomprising as ingredients a source of nickel ions, a soluble reducingagent for the nickel, a metal complexing agent and pH adjusting agentsunder conditions effective to bring about electroless deposition ofnickel on the surface or surfaces by means of chemical reduction.

[0052] Where the invention is practiced in conjunction with imagingprinting of copper lines (see co-pending application Ser. No.09/357,574, assigned to assignee of present invention), it is importantaccording to the present invention that the nickel plating be carriedout after the development of the layer of photoimageable material sinceit eliminates the possibility of electrical leakage between lines. Ifplated before the layer of photoimageable material, the presence ofnickel beneath the layer of photoimageable material could result inelectrical leakage between lines, especially when spaced relativelyclose to each other. In addition, the nickel bath is generally moreactive than a copper plating bath. Accordingly, circuitization yieldsare higher because the line will have fewer defects.

[0053] The second metallization layer is deposited by conventionalplating methods for electroless plating. These processes typically havetheir own in-line seeding means because typically it is desired to platenickel only on another metal surface. Crucial to the present inventionis that the typical precleaning/preconditioning steps normallyassociated with this electroless nickel process are not performed. Theseprocesses remove portions of the first metallization (seed) layer. Thepresent invention achieves the plating of nickel directly on thelaminate surface. Use of precleaning or preconditioning steps removesportions of the seed particles thus causing skip plating on thelaminate. Where the metal adheres to only portions of the inner surfaceof the hole, the adhesion is poor resulting is shortened mean timebetween failure.

[0054] As seen in next FIG. 6, a third metallization layer 14 isdeposited on the second metallization layer 12. This metallization layeris typically plated to the same height as the top of the photoresist,although not always. Generally, the photoresist thickness is matched tothe final desired conductor thickness. This aids post platingprocessing, if needed, for planarizing to remove plated nodules orextraneous plating above the desired conductor height should it occur.

[0055] Typically, application of the third metallization layer followssubstantially immediately after application of the second metallizationlayer. Alternatively, where it is desired to temporarily store thepartial assembly, obtained through the second metallization step, it isnecessary to clean the oxide or other inappropriate material coating thenickel prior to application of the third metallization layer. Thiscleaning may be accomplished with industry standard techniques.

[0056] It has been found that nickel, comprising the secondmetallization layer provides for enhanced adhesion of the copper to thesubstrate. Copper 14 is plated on the inner surfaces of the holes overthe nickel layer 12 from an electroless plating bath to provide thedesired PTH barrel thickness. Examples of suitable electroless copperplating baths can be found in U.S. Pat. Nos. 5,509,557, 4,707,377 and4,904,506, disclosures of which are incorporated herein by reference.

[0057] The copper electroless plating bath employed is generally anaqueous composition, which contains a source of cupric ion, a complexingagent for the cupric ion, and a pH adjustor, in addition to the cyanideion source and oxygen. In addition, the plating bath also preferablyincludes a surface-active agent. The cupric ion source generally used isa cupric sulfate or a cupric salt of the complexing agent to beemployed. The cupric ion source in the electroless plating bath istypically employed in amounts of about 9 to about 14, and more typicallyabout 10 to about 12 grams per liter, calculated as CuSo₄.5H₂O.

[0058] The most common reducing agent employed is formaldehyde. Examplesof some other reducing agents include formaldehyde precursors orformaldehyde homopolymers, such as paraformaldehyde, trioxane, andgloxal; borohydrides such as alkali metal borohydrides (sodium andpotassium borohydrides) and substituted borohydrides such as sodiumtrimethoxy borohydride; boranes such as amine borane (isopropyl amineborane and morpholine borane); and hypophosphite reducing agents. Thereducing agent is generally present in amounts from about 1 to about 4milliliters per liter, and more typically from about 2 to about 2.5milliliters per liter.

[0059] Examples of some suitable complexing agents include Rochellesalts, ethylene diamine tetraacetic acid, the sodium (mono-, di-, tri-,and tetra-sodium) salts of ethylene diamine tetraacetic acid, nitrilotetraacetic acid and its alkali salts, gluconic acid, gluconates,triethanol amine, glucono (gamma)-lactone, modified ethylene diamineacetates such as N-hydroxy ethyl ethylene diamine triacetate. Inaddition, a number of other suitable cupric complexing agents aresuggested in U.S. Pat. Nos. 2,996,408; 3,075,856; 3,076,855 and2,938,805. The preferred complexing agents are ethylene diaminetetraacetic acid and the alkali metal salts thereof. The amount ofcomplexing agent employed is typically about 25 to about 50 grams perliter.

[0060] The plating bath can also include a surfactant which assists inwetting the surface to be coated. A satisfactory surfactant is, forinstance, an organic phosphate ester, available under the tradedesignation “Gafac RE-610”. Generally, the surfactant, if present, isused in amounts from about 0.01 to about 0.3 grams per liter.

[0061] In addition, the pH of the bath is generally controlled, forinstance, by the addition of a basic compound, such as sodium hydroxideor potassium hydroxide in the desired amount to achieve the desired pH.The typical pH of the copper electroless plating bath is between 11.5and 12.0, and more typically between 11.7 and 11.9. In addition, theplating bath can include other minor additives as is known in the art.

[0062] The typical plating baths employed have a specific gravity withinthe range of 1.06 to 1.08. Moreover, the temperature of the bath istypically maintained between about 70° C. and 80° C., more typicallybetween about 70° C. and 76° C., and preferably about 72° C. to about75° C.

[0063] The copper electroless plating bath typically contains about 5 toabout 11 ppm, and more typically about 5 to about 8 ppm of cyanide ions.Examples of some cyanides are the alkali metal, alkaline earth metal,and ammonium cyanides, with sodium cyanide being a more typical example.

[0064] The electroless plating bath typically has an oxygen content ofnot lower than 1.5 ppm below saturation, and more typically an oxygencontent of not lower than 1.0 ppm below saturation.

[0065] Plating from the copper electroless plating bath generallycontinues from about 8 to about 20 hours, or until the desired thicknessof copper film is achieved, which is typically about 350 micro inches toabout 1850 micro inches. Where desired, any copper plating either majorsurface may be planarized by any standard technique including chemicalmechanical planarization (CMP).

[0066] Significantly, it can be seen that the plated through via willprovide, after removal of the photoresist, a complete and uninterruptedconductive layer around through hole 8.

[0067] In FIG. 7, the remaining portions of the photoresist layer areremoved, preferably by stripping the photoresist with a suitable solventknown in the art such as propylene carbonate, sodium carbonate, benzylalcohol, or sodium hydroxide. Other removal techniques such as laserablation and mechanical removal or combinations thereof, may also beemployed to remove the photoresist layer. In one example, the exposedareas of the first electrically conductive layer on the surfaces of basemember 13 serve as one or more contact pad areas 34. In addition to theexposed contact pad areas, it is also possible to expose one or moreareas on base member 13, depending on operational requirements for thefinal product. This area is a land segment which in turn surroundsthrough hole 8 and may serve to interconnect upper and lower layers ofcircuitry and also internal conductive planes such as 5, if desired.

[0068] It will, therefore, be appreciated by those skilled in the arthaving the benefit of this disclosure that this invention is capable ofproducing printed wiring boards having highly reliable plated throughholes. Furthermore, it is to be understood that the form of theinvention shown and described is to be taken as presently preferredembodiments. Various modifications and changes may be made to each andevery processing step as would be obvious to a person skilled in the arthaving the benefit of this disclosure. It is intended that the followingclaims be interpreted to embrace all such modifications and changes and,accordingly, the specification and drawings are to be regarded in anillustrative rather than a restrictive sense.

What is claimed is:
 1. A circuitized printed wiring board comprising: adielectric substrate provided with a pattern of vias; a firstmetallization layer located on the inner surface of said pattern ofvias; a layer of Ni deposited on said first layer; and a layer of Cuplated on said Ni layer.
 2. The circuitized printed wiring board ofclaim 1 wherein said dielectric substrate comprises epoxy resinoptionally reinforced.
 3. The circuitized printed wiring board of claim1 wherein said first metallization layer is deposited from apalladium/tin colloidal suspension.
 4. The circuitized printed wiringboard of claim 1 wherein the layer of nickel is about 1 to about 5microns thick.
 5. The printed wiring board of claim 1 wherein the layerof nickel is about 2.5 to about 3.5 microns thick.
 6. The printed wiringboard of claim 1 wherein the layer of dielectric material has aroughened surface.
 7. A method for fabricating a circuitized printedwiring board comprising: providing at least one layer of dielectricmaterial; providing a pattern of vias in said dielectric material;depositing a catalyst seed layer on said layer of dielectric material;depositing and patterning a photoresist layer on said seed layer;depositing a layer of nickel on top of said catalyst seed layer; anddepositing a layer of copper plating over said layer of nickel.
 8. Themethod of claim 7 wherein the layer of dielectric material comprisesepoxy resin optionally reinforced.
 9. The method of claim 7 wherein thecatalyst seed layer is deposited from a palladium/tin colloidalsuspension.
 10. The method of claim 7 wherein the nickel layer isdeposited to a thickness of about 1 to about 5 microns.
 11. The methodof claim 7 wherein the nickel layer is deposited to a thickness of about2.5 to about 3.5 microns.
 12. The method of claim 7 wherein the copperis deposited by electroless plating
 13. The method of claim 7, whereinelectroless plating comprises: providing a copper electroless platingbath; providing a dielectric material having PTH holes plated withnickel; and immersing said dielectric material in said electrolessplating bath.
 14. The method of claim 13 wherein said electrolessplating bath comprises oxygen not lower than 1.5 ppm below saturation15. The method of claim 13 wherein said electroless plating bathcomprises oxygen not lower than 1.0 ppm below saturation.
 16. The methodof claim 13 wherein the pH of said electroless plating bath is adjustedto the range from about 11.5 to about 12.0.
 17. The method of claim 13wherein the pH of said electroless plating bath is adjusted to the rangefrom about 11.7 to about 11.9.
 18. The method of claim 13 wherein saidelectroless plating bath comprises cyanide ion comprises from about 5 toabout 11 ppm., and more typically about 5 to about 8 ppm of cyanide ions19. The method of claim 13 wherein said cyanide ion comprises from about5 to about 8 ppm.
 20. The method of claim 13 wherein the specificgravity of said electroless plating bath is within the range of 1.06 to1.08
 21. The method of claim 13 wherein the temperature of saidelectroless plating bath is maintained between about 70° C. and 80° C.22. The method of claim 13 wherein the temperature of said electrolessplating bath is maintained between about 72° C. and 75° C.
 23. Acopper-nickel laminate via barrel obtained by the method of claim
 7. 24.A circuitized printed wiring board obtained by the method of claim 7.25. A circuitized printed wiring board comprising: a dielectricsubstrate having a top surface, and a bottom surface, and at least onevia, said at least one via having a via barrel surface and at least onevia peripheral entry surface; a first metallization layer deposited onsaid via barrel surface and said at least one via peripheral entrysurface of said at least one via, said top surface, and said bottomsurface of said dielectric substrate; a second metallization layerdeposited on said first metallization layer on said via barrel surfaceand said at least one via peripheral entry surface of said at least onevia, and selectively deposited on said first metallization layer on saidtop surface and said bottom surface of said dielectric substrate; and athird metallization layer deposited on said second metallization layeron said first metallization layer on said via barrel surface and said atleast one via peripheral entry surface of said at least one via, andselectively deposited on said second metallization layer on said firstmetallization layer on said top surface and said bottom surface of saiddielectric substrate.
 26. The circuitized printed wiring board of claim25, wherein said first metallization layer is a catalytic seed layer.27. The circuitized printed wiring board of claim 26, wherein saidcatalytic seed layer is chosen from the group consisting of palladiumand tin.
 28. The circuitized printed wiring board of claim 26, whereinsaid second metallization layer is chosen from the group consisting ofGroup VIII and Group IB transition metals.
 29. The circuitized printedwiring board of claim 26, wherein said third metallization layer ischosen from the group consisting of manganese, iron, cobalt, nickel,copper, palladium, platinum, silver, and gold.
 30. A method forfabricating a circuitized printed circuit wiring board comprising:providing a substrate having a top surface and a bottom surface;providing at least one via having a barrel surface and at least one viaperipheral entry surface in said substrate; depositing a catalyst seedlayer on said via barrel surface and said at least one via peripheralentry surface of said at least one via, said top surface and said bottomsurface of said substrate; providing a resist layer on selected areasover said catalyst seed layer on said top surface and said bottomsurface of said substrate; depositing a first metallization layer overareas of catalyst seed layer not protected by said protective resistlayer on said top surface and said bottom surface of said substrate, andsaid via barrel surface and said at least one via peripheral entrysurface of said at least one via; and depositing a second metallizationlayer over said first metallization layer.
 31. The method of claim 30wherein said step of depositing a catalyst seed layer further includesprocessing selected from the group consisting of colloidal suspension,ionic solution, and organometallic solution.
 32. The method of claim 30wherein said catalytic seed layer is palladium.
 33. The method of claim32 wherein said first metallization layer is nickel.
 34. The method ofclaim 33 wherein said second metallization layer is copper.